Modern electronic memory or data storage devices typically function as either volatile or non-volatile memory. Generally, volatile memory requires continuous power to store the memory contents, while non-volatile memory can retain data without a continuous power source. Non-volatile memory has many applications, including personal data assistants (PDAs), digital cameras, mobile phones, digital audio players, laptop computers, and other devices.
One type of non-volatile memory is “flash memory.” Generally, flash memory is a type of electrically erasable programmable read-only memory (EEPROM). Flash memory stores information in an array, and can be programmed in small, discrete increments, such as a byte or word, for example, but must ordinarily be erased in blocks larger than required in a typical EEPROM.
Some flash memory systems couple the memory to a computer system via a bus. One common bus configuration is Inter-integrated Circuit (I2C), which is particularly useful in peripheral bus systems. Generally, I2C permits multiple bus masters on a single bus. I2C is a trademark of Philips Corp.
But some current flash memory modules include only one I2C port. In some applications, technical conflicts arise when more than one I2C master attempts to access the same, one-port flash memory. Generally, the I2C protocol permits multiple bus masters, but relegates conflict detection and arbitration functionality to the bus masters.
Assigning the conflict detection and arbitration functionality to the I2C bus masters often results in the application programmer writing program code to address this issue, which increases application design cost and complexity. Further, arbitration by and between multiple bus masters can cause the I2C bus to lock up, a costly failure condition, or otherwise to become inoperative.
Another solution provides arbitration functionality through extra side-band signals. This approach, however, suffers from the drawback that it increases the number of signals, which increases design and implementation costs as well. Further, additional signals also increase power consumption.
Additionally, some applications operate with two buses on separate power boundaries. For example, one typical configuration includes a standby power domain and a main power domain. Generally, the standby power domain engages when the system couples to an external power source and, in one system, operates at 3.3V. Generally, the main power domain engages when the system powers on and, in one system, operates at 2.5V. Typical arbitration schemes that address I2C bus master arbitration fail to account for multiple power domain configurations. Known solutions that do account for multiple power domain configurations are rare, overly complicated, and expensive.
Additionally, in some applications, the I2C bus standard allows the multiple bus masters to operate under different I2C addressing protocols. For example, one bus master can run using 16-bit addressing, which most current flash memory devices use. Another bus master, coupled to the same bus, can run using legacy 8-bit addressing, which certain older flash memory devices use. Typical flash memory devices do not support multiple I2C addressing protocols.
There are a number of other features not supported by current dual-port I2C systems and methods. For example, current systems/methods do not support mixed-mode addressing. Nor do current systems/methods support multiple chips on a single I2C bus.
Therefore, there is a need for a system and/or method for dual-ported I2C flash memory devices that addresses at least some of the problems and disadvantages associated with conventional systems and methods.